Field of the Invention and Related Art Statements
The present invention relates to an image display apparatus comprising a means for controlling the input/output of image information, an image display means and a display memory which is accessed alternately by said input/output controlling means and image display means in a time division multiplex mode.
Such an image display apparatus has been known and is disclosed in Japanese Patent Publication Nos. 58-34,836 and 58-26.
FIG. 1 is a block diagram illustrating a construction of the known image display apparatus. A central processing unit (CPU) 1 for effecting an image information input/output traffic control is connected to data bus line 2 and CPU address bus line 3 through which RAM 4, ROM 5 and I/O unit 6 are connected to CPU 1. There is further provided a display memory 7 which is connected to the data bus line 2 and to an address switcher 8. To the address switcher 8 are connected the CPU address bus line 3 and a display address bus line 9 through which there is further connected a display timing generator circuit 10 for generating all the necessary timings for the display unit, CPU and others. The display memory 7 is connected via an image signal generator circuit 11 to the image display device such as CRT 12.
In case of displaying an image on the CRT 12, at first RAM 4, ROM 5 and I/O device 6 are accessed by means of a signal supplied from CPU 1. The address switcher 8 supplies to the display memory 7 alternately an input/output address supplied by CPU 1 through the CPU address bus line 3 and an display address supplied by the display timing generator circuit 10 through the display address bus line 9, in synchronism with the display timing controlled by the display timing generator circuit 10. Data to be displayed is written in the display memory 7 through the data bus line 2 under the control of an address signal supplied from CPU 1 through the CPU address bus line 2. Then the stored data is read out of the display memory 7 under the control of the address signal supplied through the display address bus line 9 and is supplied to the image signal generator circuit 11 which then produces an image signal. The image signal thus generated is supplied to CRT 12 and is displayed thereon.
FIGS. 2A to 2F are time charts for showing an operation of the known image display apparatus shown in FIG. 1. As can be seen from the drawings, in synchronism with the display timing signals (FIG. 2A) generated by the display timing generator circuit 10, the input address denoted by CPU 1 and the display address denoted by the display timing generator circuit 10 are alternately switched by the address switcher 8 in the time division multiplex mode, and the image data is entered into and then read out of the display memory 7.
In the known image display apparatus mentioned above, since the input address of CPU 1 and display address are switched alternately in synchronism with the display timing, the display timing has to be synchronized with the CPU machine cycle, and thus the access for RAM 4, ROM 5 and I/O unit 6 have to be completed within machine cycles having the same time period.
However, it is practically difficult to provide memories and I/O units having the same access time. When ROM and I/O units having longer access times are used, it is required to provide a wait time Tw in CPU 1 as illustrated in FIGS. 3A to 3F. When the wait time Tw is introduced in the machine cycle, the machine cycle is prolonged. In this case, since the access is effected for devices other than the display memory 7, an address period denoted by .circle.B in FIG. 3F is irrelevant from the image display. Therefore, an output timing of the CPU address is not synchronized with the display timing, and thus the CPU 1 could not access the display unit 7. In FIG. 3F, such an undesired condition is denoted by a reference .circle.C . During a time period denoted by .circle.C , to the display memory 7 is supplied an undesired or erroneous address represented by .circle.A in FIG. 3D. The undesired phenomenon explained above might occur not only in case of using the memory having a long access time, but also in case of effecting special functions such as multiplication and division in which the length of machine cycle varies in accordance with commands. In this manner, in the known image display apparatus it is practically impossible to provide a wait period in the CPU, so that it is impossible to utilize peripheral LSI having a longer access time. Therefore, a cost of the hardware is liable to be expensive and a serious limitation is imposed upon the function. It should also be noted that even though use may be made of devices having longer access times by providing a wait period in the CPU, the display period might be prolonged and an aspect ratio of a pixel might deviate from 1:1, because a display time of a pixel might be prolonged.